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RD_BUSY_MASTER and WR_BUSY_MASTER Operation
Figure 6-44 shows the equivalent DMA write cycle. In this case, the DMA cycle starts when WR_BUSY_MASTER is
deasserted in cycle R0.
cycle
R0
R1
A0
A1
A2
A3
0
1
2
3
4
5
6
7
8
9 10
clk
framen
cben[3:0]
6
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
reqn
gntn
mast_active
dp_start
dp_done
bar_select[2:0]
wr_cyc
wr_be_rdy
wr_be_now[3:0]
wr_busy_master
0
F
mem_add[11:0]
000
004 008
00C
mem_data_out[31:0]
0
1
2
3
Figure 6-44 · WR_BUSY_MASTER Operation
These two inputs and STOP_MASTER can be used to start and stop a DMA transfer under hardware control. Once
the DMA control registers have been programmed, the DMA can be started by deasserting the Master busy signals. It
can be stopped by asserting the Master stop and busy inputs.
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